3D VNWFET with Double Gate Stack (JL2) -Based Standard Cell Libraries

Vertical Nanowire Field Effect Transistors (VNWFET) are emerging as a promising technology to overcome the scaling limitations of conventional lateral devices. The Junction-less (JL) device with a 3D gate-all-around (GAA) architecture offers several key advantages: improved energy consumption, reduced footprint, enablement of the gate stacking approach to benefit designs with multiple transistors in series. This dataset is considered as an extension of our previous work on the generation of standard cell library based on single gate (JL1) VNWFET devices. In this work, we consider different design approach for implementing the double gate stacking (JL2): Mixed Configuration or Hybrid JL2: containing both single- and double-gate transistors (i.e. double-gate is only present in the network with two transistors in series) JL2 variants employing two gate contacts per nanowire: JL2 pure: two gates of each transistor are connected to one of the inputs JL2 G1: the bottom gates are tied to ground (resp. Vdd) in p-type (resp. n-type) devices JL2 G2: the top gates are tied to ground (resp. Vdd) in p-type (resp. n-type) devices These three configurations correspond to the networks of the cells that do not contain series transistors (i.e. single gate in previous Hybrid design), whereas the networks with initially double gates have the same design in the three above approaches. (i.e. a single input at each gate). This dataset includes the outcome of this flow presented by the liberty file of standard cell libraries based on 3D VNWFET devices while including the resistance and capacitance parasitic for the characterization of the cells. The files correspond to two threshold voltages: Regular (RVT) and Low (LVT) and composed of the following cells: BUFX1_CStatic_JL1 INVX1_CStatic_JL1 NAND2X1_CStatic_JL1 NOR2X1_CStatic_JL1 XOR2X1_CStatic_JL1 Asynch_DFFX1_CStatic_JL1 where the formalism OPnXk_Style_Technology indicates the Boolean operation OP, the number of inputs n and the drive strength k (k=1 corresponds to 4 NWs per device), as well as the logic design style (i.e., Complementary static logic obtained by using n- and p-type VNWFET) and the technology variant used to implement the cells: Junction-Less Nanowire: (JL2_Hybrid, JL2_Pure, JL2_G1_0 and JL2_G2_0). In this data set, we also provide the physical layout (in GDSII format) of the logic cells present in the generated liberty files.