A 4-bit 36 GS/s ADC with 18 GHz Analog Bandwidth in 40 nm CMOS Process

This paper presents a 4-bit 36 GS/s analog-to-digital converter (ADC) employing eighttime-interleaved (TI) flash sub-ADCs in 40 nm complementary metal-oxide-semiconductor (CMOS)process. A wideband front-end matching circuit based on a peaking inductor is designed to increasethe analog input bandwidth to 18 GHz. A novel offset calibration that can achieve quick detectionand accurate correction without affecting the speed of the comparator is proposed, guaranteeing thehigh-speed operation of the ADC. A clock distribution circuit based on CMOS and current mode logic(CML) is implemented in the proposed ADC, which not only maintains the speed and quality of thehigh-speed clock, but also reduces the overall power consumption. A timing mismatch calibrationis integrated into the chip to achieve fast timing mismatch detection of the input signal which isbandlimited to the Nyquist frequency for the complete ADC system. The experimental results showthatthedifferentialnonlinearity(DNL)andintegralnonlinearity(INL)are − 0.28/+0.22leastsignificantbit (LSB) and − 0.19/+0.16 LSB, respectively. The signal-to-noise-and-distortion ratio (SNDR) is above22.5 dB and the spurious free dynamic range (SFDR) is better than 35 dB at 1.2 GHz. An SFDR above24.5 dB and an SNDR above 18.6 dB across the entire Nyquist frequency can be achieved. With a diesize of 2.96 mm * 1.8 mm, the ADC consumes 780 mW from the 0.9/1.2/1.8 V power supply.