VerilogASTBench

Large Language Models have demonstrated strong code generation capabilities across general-purpose programming languages, yet their effectiveness on Verilog remains limited. RTL design imposes distinct challenges absent in software contexts: hardware-specific syntax, concurrent execution semantics, multi-clock timing constraints, and strict functional correctness requirements that preclude approximate outputs.To address this gap, we release a Verilog fine-tuning dataset of 168,417 samples, each pairing a structured design task description with a verified RTL implementation. The dataset is intended for instruction-supervised fine-tuning and domain adaptation of open-source language models.Coverage spans a broad range of RTL structural patterns, including interface definitions, signal declarations, procedural blocks, module instantiations, and functional implementation logic. Together, these samples provide domain-specific training signals for Verilog design tasks, enabling targeted optimization of language models toward RTL code generation and hardware design automation.