Xenn007/synth-layout-v1

---
license: apache-2.0
task_categories:
- other
tags:
- eda
- chip-design
- vlsi
- synthesis
- place-and-route
- drc
- timing
- deepgate
size_categories:
- 1B<n<10B
---

# synth-layout-v1

Multi-scale, PDK-conditioned EDA training dataset. 275K designs across 3 PDKs (Sky130, GF180MCU, ASAP7), 5 frequency targets, full RTL-to-GDS pipeline.

## Data Types

1. **technology/** - Cell library, layer stack, via definitions, design rules, RC parameters per PDK
2. **geometry_patches/** - 10x10um layout tiles with wire/via/pin/cell coordinates
3. **physics_labels/** - Per-segment R, C, coupling capacitance from SPEF
4. **drc_labels/** - Legal/illegal geometry patterns with violation type
5. **pin_access/** - Per-pin layer accessibility and obstruction data
6. **cell_neighborhoods/** - k=30 nearest cell placement context
7. **timing_contexts/** - Per-cell slew, load, delay, slack along timing paths
8. **power_grid/** - Metal mesh, via, voltage drop, current density fragments
9. **mesoscale_blocks/** - 50x50um windows with congestion and density maps
10. **global_trajectories/** - Full design state snapshots at each PnR stage
11. **deepgate/** - AIG graphs, simulation vectors, equivalence labels

## Statistics

- 275,400 valid designs
- 3 PDKs x 5 frequencies x 21,600 base designs (with mutations)
- ~1.88B training samples
- ~28TB raw, ~3.5TB compressed

## Generation

Generated using Zyphar EDA platform (Yosys + OpenROAD + KLayout + OpenSTA).