Voltage, Throughput, Power, Reliability and Multicore Scaling

This repository contains original experimental data files that support the paper "Voltage, Throughput, Power, Reliability and Multicore Scaling" published in the August, 2017 issue of IEEE Computer Magazine. http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=7999145 on IEEE Xplore and http://eprint.ncl.ac.uk/file_store/production/231220/F208FCE7-A180-417A-A442-2D14D28A0D3B.pdf on open access. The two versions have different figure numbers and the following pertains to the figure numbers in the final version of IEEE Xplore.

Any file with a name containing "FPGA" pertains to experiments on the FPGA part of a Xilinx Zynq ZC702 reported in Figures 2 and 4 of the paper.

Files with A9 in the name contains results of experiments on the pair of ARM A9 processors on the same Xilinx Zynq ZC702 system as above. This data goes to Figure 4 of the paper.

Files with names including "AnupsPC" include results from experiments on an Intel Core i7 processor. This data goes to Figure 4 of the paper.

Files with names including "A7A15", "Odroid" and pure numbers such as 1000-2000 pertain to experiments on an Odroid Xu3 system with ARM big.LITTLE processors (ARM A7 and A15 cores). This data goes to Figure 4 of the paper.

Files with "SRAM" in the names pertain to data from experiments on an asynchronous SRAM controller. This data goes to Figure 3 and Figure 4 of the paper.

Files with "phi" in the names pertain to experimental data on an Intel Xeon Phi system. This data goes into Figure 4 of the paper.

Other experimental results, pertaining to an asynchrounous 8051 microcontroller and a power-gated ARM M0 core support the findings in the paper, but because the publisher limits the total number of authors, did not make into the paper itself. This data is included in the directory with appropriately named files.

The two Matlab (.mat) files in the directory are generated from the FPGA data and are used to generate Figure 2.

本存储库包含了支持2017年8月IEEE计算机杂志上发表的论文《电压、吞吐量、功耗、可靠性和多核扩展》的原始实验数据文件。该论文可在IEEE Xplore（http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=7999145）和开放获取网站（http://eprint.ncl.ac.uk/file_store/production/231220/F208FCE7-A180-417A-A442-2D14D28A0D3B.pdf）上查阅。两个版本包含不同的图号，以下内容适用于IEEE Xplore最终版本的图号。任何文件名中包含“FPGA”的均与Xilinx Zynq ZC702的FPGA部分的实验相关，具体可参考论文中的图2和图4。文件名中包含“A9”的文件包含在上述Xilinx Zynq ZC702系统上的ARM A9处理器对的实验结果。这些数据对应论文中的图4。文件名中包含“AnupsPC”的文件包括在Intel Core i7处理器上的实验结果。这些数据也对应论文中的图4。文件名中包含“A7A15”、“Odroid”以及纯数字（如1000-2000）的文件涉及Odroid Xu3系统上ARM big.LITTLE处理器（ARM A7和A15核心）的实验。这些数据对应论文中的图4。文件名中包含“SRAM”的文件涉及异步SRAM控制器的实验数据。这些数据对应论文中的图3和图4。文件名中包含“phi”的文件涉及Intel Xeon Phi系统的实验数据。这些数据对应论文中的图4。其他实验结果，涉及异步8051微控制器和功率门控的ARM M0核心，支持论文中的发现，但由于出版商对作者总数的限制，并未包含在论文中。这些数据包含在以适当命名的文件目录中。目录中的两个Matlab（.mat）文件是由FPGA数据生成的，并用于生成图2。