Impact of Substrate Bias on Analog Performance of Dopingless Transistor

In this brief, the impact of substrate bias (Vgb),on the electrical performance of silicon on insulator dopinglesstransistor (SOI-DLT) is analyzed for analog applications. It isobserved that SOI-DLTs are more immune to Vgb in contrastto its conventional counterpart SOI junctionless transistor (SOIJLT).When Vgb is increased from 2V to 8V, the variation intransconductance (gm) of SOI-JLT is 19.22%, however, in thecase of SOI-DLT, the gm variation is 8.89%. The insignificantvariation in gm of SOI-DLT is found against Vgb than SOI-JLTdue to the use of the lightly doped channel. Further, the devicereliability of SOI DLT against impact ionization is evaluated bymeasuring the electron concentration and electric field profile.The SOI-DLT is less sensitive to impact ionization in comparisonto conventional SOI-JLT. Hence, the simulation results shownin this paper offer an opportunity for future analog integratedcircuits designing by using SOI-DLT under the influence of Vgb.