Research on Layout Optimization of Key Chips for Nuclear Safety Level DCS Based on SVR-PSO

[Background]: In order to reduce the temperature rise of the Digital Control System (DCS) key chips during operation, this study proposes a machine learning-based approach to optimize the layout of critical components. [Purpose]: The goal is to improve system reliability, especially for nuclear safety level DCS operating under accident scenarios. The research specifically focuses on key chips such as the Central Processing Unit (CPU) and Field Programmable Gate Array (FPGA), which are susceptible to significant temperature increases during abnormal operating conditions. [Methods]:  The first step involved conducting experimental tests to measure the steady-state temperatures of these chips under accident conditions, specifically at an ambient temperature of 55℃. These tests simulated extreme operational scenarios where heat dissipation was critical for the safe operation of the system. Following the experimental phase, finite element analysis (FEA) was used to simulate the test conditions. The FEA model replicated the thermal behavior of the system, allowing for a more controlled analysis of chip temperature under various layouts. Based on this model, the corresponding steady-state temperature data of the CPU and FPGA under 100 sets of random chip layouts were calculated. These data points were then used to construct a temperature prediction model using the M-SVR algorithm, which was particularly suited for predicting the nonlinear relationships between chip arrangement and temperature. By incorporating this predictive model, the study was able to predict the temperature for various chip layouts without needing to rely solely on time-consuming physical experiments or simulations. To further optimize the chip layout, the PSO algorithm was employed in conjunction with the M-SVR model. PSO, as a global optimization technique that mimics the social behavior of particles in a swarm, was highly effective for exploring large solution spaces. The PSO algorithm was used to compute the optimal coordinates for chip placement that would result in the least temperature rise, considering the complex thermal dynamics of the system. After identifying the optimal chip layout, FEA was performed again to verify the predicted results. [Results]: The consistency between the predicted and simulated results validated the accuracy of the proposed approach. The findings confirmed that the optimized layout achieved a significant reduction in chip temperature rise. Specifically, at an ambient temperature of 55℃, the steady-state temperature of the CPU decreased from 71.9℃ to 69.5℃, and the FPGA decreased from 68.4℃ to 65.9℃, corresponding to reductions of 2.4℃ and 2.5℃, respectively. [Conclusions]: This result further demonstrates the effectiveness of the proposed SVR-PSO method in improving chip layout, and thus improves the overall reliability of the DCS system. The method proposed in the research can provide guidance for solving practical engineering problems. The ability to reduce the working temperature of key chips not only improves system performance but also extends the lifespan of critical components, ultimately contributing to the reliability and safety of nuclear safety level DCS.