Mind the Portability: A Warriors Guide through Realistic Profiled Side-channel Analysis

This is supplementary dataset for our work, published in NDSS 2020, titled "Mind the Portability: A Warriors Guide through Realistic Profiled Side-channel Analysis". Brief summary about the dataset and the setup: The microcontroller is clocked at 16MHz and runs AES 128 algorithm in software. The board is connected to a two channel Tektronix TDS2012 oscilloscope with a sampling rate of 2GS/s. The power traces are captured corresponding to AES-128 execution, synchronized with a board generated trigger. A computer is used to pilot the whole setup. It generates random 128-bit plaintext and, via UART, transmits it to the board and awaits acknowledgment of the ciphertext. Upon receiving ciphertext, the software retrieves the waveform samples from an oscilloscope and saves it to hard-drive indexed with corresponding plaintext and ciphertext. To minimize the storage overhead, the trace comprised of 600 sample points captures only the execution of the first SubBytes call, i.e., the target of the following attacks (the output of the first AES S-box in the SubBytes layer).