A Pipelined Incremental ΔΣ ADC With Residue Harvesting and Noise Penalty Mitigation

This paper proposes a pipelined incremental ΔΣ analog-to-digital converter (IADC) by cascading two IADCs for sensor system-on-chip whose oversampling ratio (OSR) is constrained by the system clock frequency. The two-stage IADC disrupts the noise accumulation path of four integrations in a 2-2 multi-stage noise shaping (MASH) IADC, reducing the noise penalty from fourth-order to second-order. Consequently, the input sampling capacitor size can be reduced by 42%. And, the digital filter can be simplified significantly to reduce the overall system-level hardware cost. Two identical integrators are alternating- one integrator accumulates the quantization residue, the other one holds the residue to interface the second IADC. When one Nyquist conversion is finished, the residue is harvested by one integrator and these two integrators interchange their roles reciprocally for integration and holding the residue. Additional techniques are proposed to mitigate the circuit non-idealities. The gain self-correction technique eliminates coefficient errors in the first loop, relaxing the matching requirements of the integrator’s coefficient. Furthermore, the dynamically segmented integration combines a static lower-bandwidth amplifier with floating inverter amplifiers (FIAs) to accelerate the slewing. Fabricated in a 0.18 μm process, the prototyped IADC consumes 0.38 mm² and 470 μW under a 1.8-V supply. Clocked at a 1.6-MHz, it achieves a DR / SNDR of 98.4 dB / 95.3 dB over a 20-kHz bandwidth, resulting in FoMS,DR / FoMS,SNDR of 174.7 dB / 171.6 dB. This work validates a high-accuracy solution for low OSR applications while maintaining a competitive energy efficiency.