x86-instruction-test-vectors
收藏资源简介：
该数据集名为x86-64指令测试向量，旨在提供x86-64架构指令的真实硬件行为数据。通过在实际CPU硬件上执行每个指令编码并记录执行前后的寄存器与标志状态，数据集捕获了硅片实测行为，而非基于模型或模拟器的预测结果，因此能够反映架构文档中未定义的实现特定行为，如指令对标志位的实际影响。数据内容由x86Tester工具生成：每个测试用例针对单一指令编码，设置已知的输入寄存器和标志状态，在调试器环境中运行指令后读取输出状态。输入经过扫描以确保覆盖每个可达到的输出位。指令在固定的代码基地址（0x04000001）执行，地址相关结果已记录在输出中。数据集覆盖通用寄存器、XMM寄存器、x87 ST寄存器和标志寄存器。排除的指令类包括：MMX、YMM和ZMM（AVX和AVX-512）、掩码寄存器、绑定寄存器、瓦片寄存器、APX寄存器、具有隐式内存操作数的指令，以及非确定性或环境读取指令（如RDTSC、RDRAND和CPUID）。若主机CPU未实现某些扩展（如Intel主机上的SSE4a、XOP、FMA4和TBM），则相应指令被跳过。数据集按CPU型号组织为多个配置，每个配置对应一个独立的parquet文件，以处理器品牌字符串及其系列、型号和步进信息命名，确保不同硅片结果互不冲突。数据列包括：指令助记符（mnemonic）、完整汇编代码（asm）、指令字节的十六进制编码（encoding）、执行前寄存器/标志值的JSON映射（inputs）、执行后寄存器/标志值的JSON映射（outputs，若指令故障则为空），以及可能引发的异常类型（exception）。寄存器与标志值以原始小端字节的十六进制形式表示。该数据集适用于CPU指令集测试、逆向工程、模拟器与模型验证、编译器优化分析以及计算机体系结构研究等场景。
The dataset is named x86-64 Instruction Test Vectors and aims to provide real hardware behavior data for x86-64 architecture instructions. By executing each instruction encoding on actual CPU hardware and recording register and flag states before and after execution, the dataset captures silicon-measured behavior rather than predictions based on models or simulators, thus reflecting implementation-specific behaviors not defined in architectural documentation, such as actual effects of instructions on flags. The data content is generated by the x86Tester tool: each test case targets a single instruction encoding, sets known input register and flag states, runs the instruction in a debugger environment, and then reads the output state. Inputs are scanned to ensure coverage of each reachable output bit. Instructions are executed at a fixed code base address (0x04000001), with address-dependent results recorded in the outputs. The dataset covers general-purpose registers, XMM registers, x87 ST registers, and flag registers. Excluded instruction classes include: MMX, YMM and ZMM (AVX and AVX-512), mask registers, bound registers, tile registers, APX registers, instructions with implicit memory operands, and non-deterministic or environment-reading instructions (e.g., RDTSC, RDRAND, and CPUID). If certain extensions are not implemented by the host CPU (e.g., SSE4a, XOP, FMA4, and TBM on Intel hosts), corresponding instructions are skipped. The dataset is organized by CPU model into multiple configurations, each corresponding to a separate parquet file named with the processor brand string and its family, model, and stepping information, ensuring no conflict between different silicon results. Data columns include: instruction mnemonic (mnemonic), full assembly code (asm), hexadecimal encoding of instruction bytes (encoding), JSON map of register/flag values before execution (inputs), JSON map of register/flag values after execution (outputs, empty if the instruction faults), and the type of exception that may be raised (exception). Register and flag values are represented in raw little-endian byte hexadecimal form. The dataset is suitable for scenarios such as CPU instruction set testing, reverse engineering, simulator and model validation, compiler optimization analysis, and computer architecture research.
