Physical Coding Sublayer For 32Gbps SerDes Based On JESD204C
收藏中国科学院中国科学技术大学科学数据中心2026-01-10 收录
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资源简介：
JESD204C is the latest industry standard for interfaces between converters and logic devices.[1] The maximum rate is up to 32Gbps. In order to match such high-speed transmission, a series of 128bit parallel scrambling, CRC, and FEC circuits based on the 64/66B coding scheme has been proposed. The design was synthesized with 28nm technology by Design Compiler. It is found that the area and power consumption of the circuits are small. After tape-out, a loopback test platform was built using Xilinx's GTY IP core to verify that the system can work stably in such a high-speed mode of 32Gbps.
提供机构：
同济大学
创建时间：
2023-05-25
