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Design of a Wideband Agile Frequency Synthesizer for the S-C Band Based on DDS

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DataCite Commons2025-01-08 更新2025-04-16 收录
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https://ieee-dataport.org/documents/design-wideband-agile-frequency-synthesizer-s-c-band-based-dds
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The agile frequency source based on direct digital synthesizer (DDS) has become a critical component in high-speed frequency-hopping anti-jamming communication due to its ultra-short frequency switching time, enabling hop rates greater than code rates. This paper proposes a frequency planning method to achieve a high spectral purity agile frequency synthesizer in the range of 3.43-5.73GHz. Experimental results show that the frequency synthesizer has a switching time of less than 10ns, a spuriousfree dynamic range greater than -53dBc, and phase noise values of -91.5dBc/Hz, -92.6dBc/Hz, -101.3dBc/Hz, and -123.5dBc/Hz at frequency offsets of 1kHz, 10kHz, 100kHz, and 1MHz, respectively when outputting 4.00GHz. These results fully validate the feasibility of the proposed method.

基于直接数字合成器(DDS)的捷变频源,凭借其极短的频率切换时间,已成为高速跳频抗干扰通信领域的关键组件,可实现高于码率的跳频速率。本文提出一种频率规划方法,可在3.43~5.73GHz频段内实现高频谱纯度的捷变频合成器。实验结果表明,该合成器在输出4.00GHz信号时,切换时间小于10ns,无杂散动态范围优于-53dBc,且在1kHz、10kHz、100kHz及1MHz的频率偏移处的相位噪声分别为-91.5dBc/Hz、-92.6dBc/Hz、-101.3dBc/Hz与-123.5dBc/Hz。上述结果充分验证了所提方法的可行性。
提供机构:
IEEE DataPort
创建时间:
2025-01-08
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