Replication Data for A Multi-Self-Cascoded Voltage Reference with 2.73-ppm/V Line Sensitivity and 20.1-ppm/°C Temperature Coefficient at 0.45-V Supply

This dataset includes results of extensive electrical simulations of a novel CMOS voltage reference circuit, based on a multi-self-cascoded topology, optimized for ultralow-voltage and ultralow-power operation in combination with energy-harvested sources. Such simulations have been performed with the Spectre electrical simulations in post-layout conditions, using device models of a 180-nm CMOS process provided by the silicon foundry. Performed simulations focused on robustness against process-voltage-temperature (PVT) variations, as a standardized validation step in view of integrated-circuit fabrication. Files in Comma-Separated Values (CSV) format obtained from such simulations are included in the dataset and described in this file. promising results for applications of the proposed circuit in ultralow-voltage have been obtained, ultralow-power electronic devices for environmental monitoring and smart agriculture.