"Asynchronous Circuit Logic Dataset (ACLD)"

"Asynchronous Circuit Logic Dataset (ACLD)A comprehensive collection of asynchronous circuit logic designs, featuring 4 pipeline structures and 26 asynchronous design templates based on 6 data channel configurations. The dataset contains 120 asynchronous circuit logic designs, serving as a valuable resource for simulating and evaluating diverse asynchronous design methods.Table of ContentsDataset OverviewQuick StartProject StructureDataset StatisticsDataset QualityScripts UsageContributingLicenseContactDataset OverviewThis dataset contains high-quality asynchronous circuit logic from various pipeline structures and design templates. It is organized for easy access and analysis.Quick StartClone the repository and explore the dataset:# Clone the repository git clone https:\/\/github.com\/your-repo\/ACLD.git cd ACLD # Example: Extract circuit logic properties python Scripts\/genLogicJson.py --input [repoID].sp --output [repoID].jsonProject StructureACLD\/ \u251c\u2500\u2500 ACLD\/                                 # Main dataset directory \u2502   \u251c\u2500\u2500 1_10.1109-ASYNC.2010.11_ACL\/         # #1 circuit logic from DOI (10.1109\/ASYNC.2010.11) \u2502   \u2502   \u251c\u2500\u2500 [repoID].json                    # Circuit logic description file \u2502   \u2502   \u251c\u2500\u2500 [repoID].sp                      # SPICE netlist file \u2502   \u2502   \u251c\u2500\u2500 [repoID]_tb1.sp                  # Testbench file (transient) \u2502   \u2502   \u2514\u2500\u2500 [repoID]_tb2.sp                  # Testbench file (DC) \u2502   ... \u2502   \u2514\u2500\u2500 120_10.1109-ASYNC.1996.494434_ACL\/   # #120 circuit logic from DOI (10.1109\/ASYNC.1996.494434) \u2502       \u251c\u2500\u2500 [repoID].json                    # Circuit logic description file \u2502       \u251c\u2500\u2500 [repoID].sp                      # SPICE netlist file \u2502       \u251c\u2500\u2500 [repoID]_tb1.sp                  # Testbench file (transient) \u2502       \u2514\u2500\u2500 [repoID]_tb2.sp                  # Testbench file (DC) \u2502   ... \u251c\u2500\u2500 Scripts\/                    # Utility scripts \u2502   \u251c\u2500\u2500 genLiteratureJson.py    # Publication information collection and parsing \u2502   \u251c\u2500\u2500 genLogicJson.py         # Circuit logic property extraction \u2502   \u2514\u2500\u2500 getMetadata.py          # Publication metadata collection from IEEE \u251c\u2500\u2500 Logic.txt                   # List of target circuit logics for collection \u251c\u2500\u2500 README.md                   # Dataset documentation and analysis report \u2514\u2500\u2500 LICENSE                     # Project license informationDataset StatisticsItemCountPipeline Structures4Design Templates26Data Channel Configs6Total Circuit Logics120For a summary of asynchronous circuit logic, see Logic.txt.Dataset QualityAll circuit logics are verified for completeness.JSON and netlist files are organized by logic type and source.No empty or corrupted files are included.Scripts UsagegenLiteratureJson.py: Collects and parses publication information.Example: python Scripts\/genLiteratureJson.py --input input_file --output output_filegenLogicJson.py: Extracts circuit logic properties from SPICE netlists.Example: python Scripts\/genLogicJson.py --input [repoID].sp --output output.jsongetMetadata.py: Retrieves publication metadata from IEEE.Example: python Scripts\/getMetadata.py --doi 10.1109\/ASYNC.2010.11 --output metadata.jsonNote: Scripts require Python 3.x. Install dependencies as needed (see script headers for requirements).ContributingContributions to expand the dataset are welcome! You can:Add new asynchronous design characteristicsImprove annotation qualityAdd more circuit logics to existing design characteristicsPlease open a pull request or issue for discussion.LicenseThis dataset is licensed under the Creative Commons Attribution 4.0 International License.You are free to:Share \u2014 copy and redistribute the material in any medium or formatAdapt \u2014 remix, transform, and build upon the material for any purpose, even commerciallyUnder the following terms:Attribution \u2014 You must give appropriate credit, provide a link to the license, and indicate if changes were made.For more details, see the LICENSE file.How to CiteIf you use this dataset in your research or publication, please cite the relevant article associated with the dataset. Use the following BibTeX format as a template:@article{ACLD2025,  title=\"{Descriptor: Asynchronous Circuit Logic Dataset (ACLD)}\",  author={Ji, Yuxin and Du, Haochen and Wang, Chao and Hou, Yuting and Li, Yongfu},  note = {Manuscript under review, IEEE Data Descriptions},  year = {2025} }ContactFor questions and support, please open an issue in the repository."