Interface engineering in two-dimensional transistors: current status and challenges

The development of silicon-based semiconductors in line with Moore’s Law is fast approaching its fundamental physical limits, posing a critical challenge to the continued miniaturization and performance enhancement of traditional electronic devices. In this context, two-dimensional (2D) semiconductors such as MoS2, WSe2 and black phosphorus have emerged as highly promising candidates as the channel materials for constructing next-generation electronic devices, owing to their unique atomic-scale thickness, exceptional semiconductor properties, and superior electrostatic tunability. Despite the great potential of 2D transistors to achieve groundbreaking performance at the atomic scale, their actual device performance has fallen far short of theoretical expectations. A primary contributing factor lies in the ultra-thin bulk thickness of 2D Mater, which renders them extremely sensitive to the surrounding interface environment. When integrated into transistor devices, a series of interface-related issues arises, severely hindering the improvement of device performance. Consequently, the realization of high-quality interface contacts has become a pivotal measure to break through the performance and integration bottlenecks of 2D electronic devices. Building on this context, this article presents a systematic review of several key interfaces in 2D transistors, with a specific focus on the metal electrode/2D semiconductor interface, the dielectric layer/2D semiconductor interface, and the encapsulation layer (substrate)/2D semiconductor interface. For each interface type, the review first analyzes the critical challenges currently faced, then introduces the relevant interface optimization strategies, and finally summarizes the latest research progress in enhancing interface quality. In the case of the metal electrode/2D semiconductor interface, regulating the contact barrier and improving carrier injection efficiency are core objectives. To address issues like Fermi level pinning (FLP) and high contact resistance, two approaches, including residue-free transfer of 2D Mater and the formation of van der Waals (vdW) contacts, have been experimentally validated as highly effective. For the dielectric layer/2D semiconductor interface, the main challenge is to suppress carrier scattering caused by impurities and defects, which degrades carrier mobility. Additionally, the intrinsic lack of dangling bonds on the surface of 2D Mater makes the deposition of high-quality dielectric layers difficult, and the structural incompatibility between traditional three-dimensional (3D) dielectric materials and 2D semiconductors further exacerbates interface problems. To overcome these hurdles, a range of strategies has been proposed, including surface passivation, the introduction of molecular crystal buffer layers, the adoption of 2D dielectric layers and in-situ oxidation. Furthermore, the atomic-scale thinness of 2D semiconductors makes them highly vulnerable to external environmental factors, leading to severe performance degradation over time. Thus, effective encapsulation and the use of flat substrates are crucial for ensuring the long-term stability and reliable performance of 2D transistors. Among various encapsulation materials, 2D hBN stands out as the optimal choice for both encapsulation layers and substrates. This is attributed to its atomically flat surface and excellent ability to block small-molecule contaminants. Overall, the content of this review covers multiple critical aspects of 2D transistor interface engineering, including contact engineering, dielectric engineering, surface encapsulation and substrate optimization. In addition, the article also provides an outlook on the future development directions of this field, such as further reducing the vdW gap between the electrode and the 2D semiconductor to enhance the carrier injection efficiency, developing vdW dielectric materials with high dielectric properties and matching them with large-scale integration processes, as well as optimizing the vdW integration method to achieve device integration without damaging the two-dimensional semiconductor. The primary aim of this review is to clarify the crucial role of interfaces in 2D transistors and to emphasize that releasing the full potential of 2D semiconductors relies heavily on improving interface quality. By addressing interface-related challenges, this work seeks to accelerate the translation of 2D semiconductor technology from experimental research to practical industrial applications, paving the way for the next era of high-performance electronics.