Graph-Aware Post-Export Channel Alignment for Efficient Neural Network Inference on Arm Cortex-M

This dataset accompanies “Graph-Aware Post-Export Channel Alignment for Efficient Neural Network Inference on Arm Cortex-M.” It contains the artifacts used to apply and check a post-export ONNX channel-alignment repair for CMSIS-NN: original and repaired ONNX models (including INT8 QDQ pairs for two CIFAR-10 classifiers), transformation and validation code, STM32F407 firmware images and sources, 20-repeat interleaved DWT latency captures with campaign summaries, processed tables, and host-side correctness reports. Official MLPerf Tiny weights, CIFAR-10 images, and the CMSIS-NN source tree are not redistributed; CMSIS-NN was used at commit 6d9d61d8a586c39160d0c1ba58f6948e4cf61ad0. Hardware timings are for STM32F407 @ 168 MHz. The accompanying paper reports 5.5–9.8% lower summed-layer latency on the constructed primary-suite profiles, 8.35% and 4.36% lower end-to-end cycle counts on two trained CIFAR-10 classifiers, and a synthetic stress case in which high MAC overhead increases latency. Interpret results only for the included models, that CMSIS-NN snapshot, and this board/toolchain configuration.