Emulating transient ASIC faults in AMD Ultrascale+ FPGA: MC8051 and NOEL-V processors as a case study

This dataset contains the results of FPGA fault injection experiments targeting MC8051 and NOEL-V soft-core processors implemented in AMD Zynq Ultrascale+ and AMD Virtex Ultrascale+ FPGAs respectively. Experiments consider fault models representative for ASIC designs, including bit-flips in the registers (CLB Flip-Flops) and on-chip RAM (BRAMs). Fault injection experiments are automated by means of BAFFI fault injection tool. The obtained results are validated by means of simiualtion-based fault injection experiments (SBFI) in RTL and gate-level models of the considered processors. SBFI experiments are automated by means of the DAVOS-SBFI tool. Both BAFFI and DAVOS-SBFI tools are available as a part of DAVOS fault injection toolkit at https://gitlab.com/selene-riscv-platform/DAVOS. The detailed description of the dataset is provided in the attached Readme.pdf.