DET Flip Flop Usage with Commercial Cad Tools (Synthesis, P&R and Cell Characterization)

A novel ultra-low-voltage (ULV) Dual-EdgeTriggered (DET) flip-flop based on the True-Single-PhaseClocking (TSPC) scheme is presented in this paper. Unlike Single-Edge-Triggering (SET), Dual-Edge-Triggering has the advantage of operating at the half-clock rate of the SET clock. We exploit the TSPC principle to achieve the best energy-efficient figures by reducing the overall clock load (only to 8 transistors) and register power while providing fully static, contention-free functionality to satisfy ULV operation. The proposed DET design only requires 28 transistors, which is the lowest number reported among the state-of-the-art dual-edge designs. At 0.5V near-Vth level in 65nm bulk CMOS technology, the proposed DET-FF demonstrates up to 25-39% and 16-42% of energy efficiency at 0% and 100% data activity rates compared to the most reliable DET-FFs when measured at cell level. Moreover, for the first time, we provide a VLSI integration methodology with design automation support to use DET flip-flops with commercial CAD tools. From integration and post layout simulations, we observed energy savings upto 43% for a 320-bit shift register and upto 28% for a RISC-V processing core at near-VTH and at nominal VDD levels, respectively. This data package contains scripts, automated tool support for the DET flip-flop integration into larger digital designs.

本文提出了一种基于真实单相时钟（TSPC）方案的全新超低电压（ULV）双沿触发（DET）触发器。与单沿触发（SET）相比，双沿触发具有在SET时钟一半速率下运行的优点。我们利用TSPC原理，通过降低整体时钟负载（仅8个晶体管）和寄存器功耗，同时提供完全静态、无冲突的功能，以满足ULV操作需求，从而实现了最佳能效比。所提出的DET设计方案仅需28个晶体管，这在现有的双沿设计方案中是最少的。在65nm体硅CMOS技术下，0.5V近Vth电平处，与最可靠的DET-FF相比，在0%和100%的数据活动率下，所提出的DET-FF在单元级测试中表现出高达25-39%和16-42%的能效。此外，我们首次提供了一种VLSI集成方法及设计自动化支持，以利用商业CAD工具实现DET触发器的集成。从集成和后布局仿真中观察到，在近VTH和标称VDD电平下，320位移位寄存器能节省高达43%的能量，而RISC-V处理核心能节省高达28%的能量。本数据包包含脚本以及将DET触发器集成到更大数字设计中的自动化工具支持。