Reliability-aware and low power design techniques

As CMOS transistors are scaled toward ultra deep submicron technologies, circuit reliability will be one of the most important challenges in the following years for the semiconductor industry. Reliability is defined as the ability of a circuit to satisfy its specifications over a specified period of time under particular conditions. ❧ Circuit reliability issues can be categorized in two parts. One is the aging effects and the other one is the transient effects. Aging effects are the problems which arise during circuit operation over the time. Negative-Bias Temperature Instability (NBTI), Hot Carrier Injection (HCI), Time Dependent Dielectric Breakdown (TDDB) and Electromigration (EM) are the most important aging problems in today’s VLSI design. Transient effects are the temporary problems which happen during the circuit operation. The most famous one is the soft error. ❧ On the other hand, one of the other most important challenges in today’s IC design is the dramatic increase in the power consumption of the electronic devices. This has made the energy efficiency of circuit components and computing systems a very important concern. Energy efficiency is especially desirable for portable electronics (e.g., mobile phones, laptops, tablets, etc) because it lengthens the battery lifetime. Almost half of the total chip power consumption is due to leakage power at deep submicron technology nodes; hence, leakage power consumption plays a substantial role in the energy efficiency of the circuits. ❧ This dissertation is divided into two parts. In the first part, we discuss the reliability effects. First we go over soft error as a transient reliability issue and consider the effect of event upsets caused by energetic particle hits. We show that the conventional analysis of this effect in sequential circuit elements tends to underestimate the threat posed by such events. A transistor- level sizing technique is introduced to solve the problem. Later, NBTI as an aging process is introduced. The effect of NBTI on the setup and hold timing constraints imposed on the flip-flops in the design is investigated. Next, we introduce a multi-corner optimization problem to minimize the energy-delay product of the flip-flops. ❧ The second part of this dissertation is focused on leakage power minimization. Timing analysis during synthesis and physical design is pessimistic, which means there are some slacks available to be traded for leakage power minimization. We introduce our post sign-off leakage power minimization technique to take advantage of these slacks. In this approach, the available slack can be traded for leakage power minimization by footprint-based cell swapping and threshold voltage assignment.