"CORE-CC: A Corpus of Synthesizable Verilog RTL Modules Dataset for Error Correction Code "

"The CORE-CC (Corpus of Synthesizable Verilog RTL Modules Dataset for Error Correction Code) is a comprehensive, open-source dataset containing 26 parameterized error-correction code (ECC) architectures, designed for fault-tolerant computing research and Design-Technology Co-Optimization (DTCO). The dataset covers a broad spectrum of ECC schemes, ranging from fundamental architectures (Parity, Hamming SECDED) to advanced algebraic and capacity-approaching algorithms (BCH, Reed-Solomon, LDPC, Turbo, and Polar).It features a robust dual-domain implementation: \"Golden Reference\" Python algorithms that define and validate the precise mathematical logic, accompanied by corresponding synthesizable Verilog RTL modules. All hardware implementations are rigorously validated for functional correctness using cycle-accurate Verilator co-simulation C++ testbenches and evaluated for hardware latency and area overhead (logic cell cost) via Yosys logic synthesis. The compiled dataset includes extensive performance metrics across diverse data widths (4 to 128+ bits) and injected error patterns (single, double, burst, random). Ultimately, CORE-CC serves as a standardized benchmark workload for EDA tool evaluation, a ready-to-deploy repository of open soft IP for SoC and FPGA prototyping, and an educational platform for digital hardware design."