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"Adaptive threshold block matching 3D denoising algorithm based on ASIC implementation Data Comparison"

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DataCite Commons2026-03-16 更新2026-05-03 收录
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https://ieee-dataport.org/documents/adaptive-threshold-block-matching-3d-denoising-algorithm-based-asic-implementation-data-0
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"The denoising effect of dedicated integrated circuits on input video images is of great significance for improving the encoding efficiency of subsequent video images, as well as for target recognition and tracking. The image denoising algorithm based on ASIC needs to balance the denoising effect, hardware overhead, and system bandwidth. Therefore, this article proposes a block matching 3D denoising algorithm ATBM3D based on ASIC for adaptive threshold filtering of Y component. This algorithm has made three improvements to BM3D computation. Firstly, in order to preserve as much detail and texture information as possible in the original image, we improved the frequency domain coefficient adaptive calculation of the Hard Threshold(HT) based on the first patch after 3D transformation, while supporting fine tuning of the denoising threshold; Secondly, using step size optimization block matching grouping to solve the throughput mismatch problem caused by the expansion of input data and 3D filtering data, while reducing hardware implementation resource overhead; Thirdly, in order to achieve real-time pipeline processing, near memory SRAM is used to cache search window information. At the same time, the 3D filtering process uses a 2-fold clock to balance the pressure of filtering throughput caused by block matching. The ATBM3D algorithm in this article has been implemented using ASIC hardware and other self-developed ISP algorithms based on TSMC6nm process chip fabrication. With a scale of one million gate level circuits, the chip debugging effect can achieve good noise reduction, and at the same time, video image processing has been achieved 4K@60fps Real time processing."
提供机构:
IEEE DataPort
创建时间:
2026-03-16
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