Evidence Package: Wire-Level Interrupt-to-Decision Latency of On-Sensor MLC versus Host Inference on the NVIDIA Jetson Orin Nano (SENSL-26-06-RL-0906, Revision 1)

Name: Evidence Package: Wire-Level Interrupt-to-Decision Latency of On-Sensor MLC versus Host Inference on the NVIDIA Jetson Orin Nano (SENSL-26-06-RL-0906, Revision 1)
Creator: Zenodo
Published: 2026-09-25T05:14:05+08:00

Zenodo2026-09-25 更新2026-10-01 收录

数据链接：

https://zenodo.org/doi/10.5281/zenodo.22950120 数据链接链接失效反馈

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资源简介：

Raw Saleae captures, tegrastats/sweep logs, and verification code evidencing the three-transaction bank-switch MLC read (362/362 decision windows verified on the wire) and the interrupt-to-decision latency decomposition reported in SENSL-26-06-RL-0906 Revision 1. Includes gate-passing blocks captured under nvpmodel mode 3 (MAXN_SUPER_JC) per pre-registration v7.6 Change 2, the gate-failing dynamic-regime blocks retained as a labeled secondary regime, and the confirmatory reference block. Verification is stdlib-only: python3 code/analysis/i2c_window_decode.py full data/block-b005-mlc-idle reproduces 62/62; regeneration instructions for excluded multi-GB intermediates are in the README.

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Zenodo

创建时间：

2026-09-25