architect-ubc-capstone/rtl-augmented-v2

--- license: mit task_categories: - text-generation tags: - rtl - verilog - bug-fix - sft size_categories: - 1K<n<10K --- # RTL Bug Fix — Augmented Dataset Auto-generated dashboard snapshot (2026-03-22T01:59:38). ## Overview | Metric | Value | |--------|-------| | Total problems | 795 | | Repos with data | 8 / 81 | | Modules augmented | 66 | | Bug types | 8/8 | | Augmentation success | 80.2% | ## Coverage  ## Distribution   ## Augmentation Health  ## Topic Coverage  ## Warnings - missing_else_latch: underrepresented (30 problems, 3.8%) - operator_typo: underrepresented (51 problems, 6.4%) - No augmentation data for topics: ai, altera, arquitetura, asic, chisel, computer-architecture, core, cpu, crypto, cryptography, dlx, embedded, embedded-systems, formal-verification, fpga-soc, gtkwave, hardware-designs, hdl, instruction-set-architecture, ise, microprocessor, mips, mit-license, nuclei, open-source, pipeline, processor, python, questasim, research-project, riscv, riscv32, riscv64, rtl-design, rv32, rv32i, simulation, soc, spi, spi-interface, synthesis, system-on-chip, testbench, uart, verification, verilator, vhdl, vivado, vlsi, vlsi-design, xcrypto - 73/81 discovered repos have zero augmentation data