Project "Tiansuan": A Tri-Thread Helical Chip Architecture for the Post-Silicon Era (Preprint · Part I:Overview & Photonic Chip)

We propose "Project Tiansuan"—a tri-thread helical chip architecture for the post-silicon era. The architecture simultaneously advances three technological threads—photonic chips, quantum-classical hybrid chips, and carbon-based neuromorphic chips—and explores their fusion via 3D heterogeneous integration. As silicon CMOS approaches its physical limits, the paradigm for next-generation chips may not lie in extending Moore's Law along a single physical path, but in allowing different physical carriers to perform their respective roles. This preprint, as Part I, presents the technical overview and the photonic chip execution manual. All performance parameters are design targets or theoretical estimates with uncertainty ranges noted. We welcome calibration feedback from both industry and academia. Keywords: Photonic chip; Quantum-classical hybrid chip; Carbon-based neuromorphic chip; 3D heterogeneous integration; Post-silicon era