Design of low-power and resource-efficient on-chip networks

Many‐core processors will continue to proliferate in the next decade across the entire computing landscape. While on‐chip networks provide a potentially scalable interconnection solution for many‐core chips, they present serious challenges in achieving the power and resource‐efficiency needed for satisfying the constraints of future chip multiprocessors. This dissertation explores the opportunities, challenges and viable solutions at the architecture‐level in designing low‐power and resource-efficient on‐chip networks. ❧ This research provides insight into the key factors affecting the effectiveness of power‐saving techniques, particularly as it relates to power‐gating on‐chip network routers. Two schemes are proposed that effectively decouple computational and communication resources to maximize static power savings while also minimizing performance penalty by dynamically powering on/off resources based on runtime application traffic load. The two schemes are generally applicable to direct network and indirect network topologies, respectively. ❧ This research also addresses the challenging problems that remain in reducing the resource requirements of on‐chip networks, which also affect power efficiency. This work investigates different ways of conveying global information using only local resources to solve a couple of difficulties that have hindered efficient flow control designs in virtual cut‐through and wormhole‐switched networks for over a decade. The proposed theoretical support and implementation schemes are applicable to a broad set of network designs to ensure freedom from both routing‐induced and protocol‐induced deadlock, thus having important theoretical value and practical applications. ❧ This research also investigates the compelling opportunities for recognizing and exploiting the emerging regional traffic behaviors exhibited in on‐chip networks. The proposed schemes for enhancing resource utilization, along with the previous resource minimizing schemes, allows more on‐chip resources to be powered off dynamically, thus widening the entire spectrum of trade‐offs among power, resource and performance.