A 161mW 32Gb/s ADC-Based NRZ SerDes Receiver Front End in 28nm

A 32-Gb/s NRZ ADC-based SerDes receiver front end is presented in TSMC 28nm process. The front end consists of a degenerated CML combined with Gm-TIA ontinuous Time Equalizer (CTLE) which provides equalization, gain as well as buffering at 16GHz, followed by a 32-way time-interleaved Analog-to-Digital Converter (TI-ADC), which is implemented in a 4x8 hierarchy. The Gm-TIA structure is utilized as an active inductor, combined with neutralization capacitor, achieving required bandwidth without using passive inductor. The gain, offset and sample clock error calibrations are implemented. This proposed front end operates at 32Gb/s achieving SNR of 36.4dB and SFDR 46.25dB at lower frequency; 29.65dB and 41.52dB respectively at Nyquist, consuming 161mW combined.