Design and Optimization of E-Mode AlN FETs Featuring p-NiOx Gate Stack and Junction Termination Extension
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https://ieee-dataport.org/documents/design-and-optimization-e-mode-aln-fets-featuring-p-niox-gate-stack-and-junction-0
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This work demonstrates a novel enhancement-mode (E-mode) AlN-channel FET utilizing a recessed p-NiOx gate stack and an optimized junction termination extension (JTE). The electrons beneath the gate electrode are effectively depleted by the recessed p-NiOx gate. TCAD simulations reveal that the synergistic optimization of gate-recess geometry and JTE parameters enables a record-high breakdown voltage (VBR) of 7140 V and a remarkable power figure of merit (PFOM) of 5.46 GW\/cm2 . These results significantly surpass reported \u03b2-Ga2O3 and GaN-channel devices. Furthermore, the high thermal conductivity of AlN ensures superior thermal management, with a minimal lattice temperature rise of only 5 K at peak power. This study provides a critical design framework for next-generation kilovolt-class ultra-wide-bandgap power electronics.
提供机构:
Yinhe Wu



