FVLLMONTI Application examples: Single reconfigurable VNWFET TCAD simulation and Reference logic cell DTCO flow

This data set presents two application examples collecting and highlighting some of the key components to the TCAD, compact modelling and DTCO approaches carried out as part of the FVLLMONTI project in relation to Deliverable D3.2.

First we present an example that demonstrates the functionality of the U-shaped reconfigurable transistor, switching the device behaviour between NMOS and PMOS using the Program Gate and giving the transistor characteristics of those devices.

Secondly, this data set gives an introduction into the FVLLMONTI DTCO approach. The provided simulation project shows a reference DTCO flow from layout to library characteristics for previously delivered physical logic cell designs. The DTCO flow provides insight into logic cell parasitics, netlist for 3rd party SPICE analysis, and KPI determination and characterization.

Both simulation projects can be seen as template for similar setups employed to overcome the challenges and answer the detailed questions faced in investigating a newly developed semiconductor technology such as the FVLLMONTI stack.