Back-Side SEM Images and Respective Modified GDSII Chip Designs

This data set consists of backside scanning electron microscope (SEM) images of four different CMOS integrated circuits (90nm, 65nm, 40nm and 28nm technologies) recorded for this study. The images are tiled with a 10% overlap and arranged in a grid according to their respective file names (Tile_001-YYY-XXX-[...].tif). More precise coordinates generated by stitching can be found in the file "stitching.zip" which is included in the data set, as well as in the corresponding GitHub repository. Additionally, the data set contains the GDSII design files of all imaged chips, although only an abstracted version. The abstracted design files contain only the standard cell area and furthermore only the bounding boxes of the cells with anonymized identifiers. Some of the identifiers contain the keyword "FILL_" denoting a filler cell. Identifiers not containing the keyword refer to functional standard cells. Identical identifiers also denote identical cell types. As detailed in our study, each of the GDSII files is trojanized in the sense that it contains 10 manipulations where cells have been exchanged by different cells of the same size (4 filler cell replacements and 6 standard cell replacements). The positions of the modifications on each chip are neither revealed in our study nor in this data set. Yet, verification of your own detection results should be possible to some extent with the image cutouts provided in the appendix of the study. Should the exact positions be needed for related research, or should the benign, untrojanized files be required, do not hesitate to contact the authors. Software and details how to use the dataset can be found in the respective GitHub repository at the following URL: https://github.com/emsec/ChipSuite Please make sure to always cite our study when using any part of our data set or code for your own research publications! @inproceedings {2023puschner, author = {Endres Puschner and Thorben Moos and Steffen Becker and Christian Kison and Amir Moradi and Christof Paar}, booktitle = {2023 IEEE Symposium on Security and Privacy (SP)}, title = {Red Team vs. Blue Team: A Real-World Hardware Trojan Detection Case Study Across Four Modern CMOS Technology Generations}, year = {2023}, pages = {763-781}, keywords = {hardware-trojans;very-large-scale-integration;gdsii;integrated-circuits-verification}, doi = {10.1109/SP46215.2023.00044}, url = {https://doi.ieeecomputersociety.org/10.1109/SP46215.2023.00044}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, month = {may} }

本数据集包含针对四种不同CMOS集成电路（90nm、65nm、40nm和28nm工艺技术）的后侧扫描电子显微镜（SEM）图像，这些图像是为本研究而记录的。图像以10%的重叠进行拼接，并按照各自的文件名（Tile_001-YYY-XXX-[...].tif）排列成网格状。通过拼接生成的更精确坐标可在数据集中包含的“stitching.zip”文件中找到，亦可在相应的GitHub仓库中找到。此外，数据集还包含了所有成像芯片的GDSII设计文件，尽管仅为抽象版本。抽象设计文件仅包含标准单元区域，且仅包含带有匿名标识符的单元的边界框。部分标识符包含关键词“FILL_”，表示填充单元。不包含该关键词的标识符则指代功能标准单元。相同的标识符也代表着相同的单元类型。正如我们的研究所述，每个GDSII文件均经过特洛伊木马化处理，其中包含10次操作，即通过不同尺寸的单元替换原有单元（4个填充单元替换和6个标准单元替换）。每块芯片上修改的位置既未在研究中披露，也未在本数据集中公开。然而，借助研究附录中提供的图像切片，在一定程度上可以验证您的检测结果。若相关研究需要精确的位置信息，或需要无特洛伊木马化的良性文件，请勿犹豫，及时联系作者。有关软件和数据集的使用细节可在以下GitHub仓库中找到：https://github.com/emsec/ChipSuite。在使用本数据集或代码的任何部分进行自己的研究发表时，请务必引用我们的研究！@inproceedings {2023puschner, author = {Endres Puschner and Thorben Moos and Steffen Becker and Christian Kison and Amir Moradi and Christof Paar}, booktitle = {2023 IEEE Symposium on Security and Privacy (SP)}, title = {红队与蓝队：跨越四个现代CMOS技术代际的真实世界硬件特洛伊木马检测案例研究}, year = {2023}, pages = {763-781}, keywords = {硬件特洛伊木马；超大规模集成电路；GDSII；集成电路验证}, doi = {10.1109/SP46215.2023.00044}, url = {https://doi.ieeecomputersociety.org/10.1109/SP46215.2023.00044}, publisher = {IEEE计算机学会}, address = {Los Alamitos, CA, USA}, month = {五月}}