Figures of merit that characterize silicon gate-all-around nanowire FETs affected by line edge roughness variability

Off-current, threshold voltage, sub-threshold slope and on-current values for two silicon gate-all-around nanowire FETs affected by line edge roughness (LER) variability, a 22 nm gate length device and a 10 nm gate length one. The LER profile that characterizes the roughness deformation is also included in the dataset. Different correlation length (CL) and root mean square (RMS) heights values are characterized.