PROJECT VORTEX-ION: In-Situ Pyro-Catalytic Filter Loop (Model VXI-4000)

================================================================================ **ZENODO METADATA PROFILE: PROJECT VORTEX-ION** ================================================================================**[PROJECT OVERVIEW]** Project Title: PROJECT VORTEX-ION: In-Situ Pyro-Catalytic Filter Loop (Model VXI-4000) Authors/Creators: Jacoby, Zachary August **[ZENODO REPOSITORY TITLE]** An Asymmetric Multiprocessing (AMP) Framework and Hardware Isolation Protocol for Co-Located In-Situ Real-Time Safety Core Monitoring on Dual-Core Silicon--------------------------------------------------------------------------------**ABSTRACT / TECHNICAL SUMMARY**-------------------------------------------------------------------------------- This repository contains the complete, production-certified bare-metal source tree, absolute linker maps, memory safety drivers, and hardware deployment scripts for Project Vortex-Ion. This architecture implements a highly deterministic, co-located in-situ safety core monitoring framework running on the STMicroelectronics STM32H747 dual-core ARM Cortex-M7/M4 microcontroller. The primary objective of this subsystem is the real-time, zero-latency parsing of critical in-situ industrial process telemetry (including pyrometer thermal arrays, nitrogen curtain purge pressures, and differential filter profiles) inside high-hazard environments. To achieve absolute reliability, the architecture enforces a strict Asymmetric Multiprocessing (AMP) sandboxing layout. The Cortex-M4 secure safety core is entirely air-gapped into isolated RAM (SRAM4), operating with zero dependencies on primary Flash or System SRAM, completely decoupling it from the non-deterministic, high-overhead material and economic projection models executing concurrently on the 480 MHz Cortex-M7 master core. -------------------------------------------------------------------------------- **KEY MICROARCHITECTURAL & ISOLATION FEATURES** -------------------------------------------------------------------------------- * **IN-SITU TELEMETRY CACHE ALIGNMENT**: The shared in-situ telemetry data structure (VXI_InSitu_Telemetry_t) is meticulously serialized, packed, and balanced to measure exactly 32 bytes (the precise length of an ARM L1 data cache line). This geometry completely eliminates multi-core cache-line thrashing and allows the Cortex-M7 application core to perform unified, single-instruction cache maintenance (mcr p15 coprocessor instructions) directly to the Point of Unification (PoU) at the physical SRAM4 boundary. * **C11 HARDWARE-FENCE ATOMICS**: Multi-core race conditions and shared bit-erasure are neutralized via strict C11 hardware atomic intrinsics (__atomic_store_n / __atomic_or_fetch). This forces the compiler to generate true LDREX and STREX assembly structures arbitrated by the system interconnect's Global Exclusive Monitor, protecting the volatile shared telemetry memory domain during simultaneous multi-core read-modify-write operations. * **BI-DIRECTIONAL MULTI-CORE MPU ISOLATION**: Domain sandboxing is secured symmetrically across both processor matrices. The Cortex-M4 core enforces a 3-slot Memory Protection Unit (MPU) layout consolidating its 48KB executable code space into a single slot (Region 0) via a Sub-Region Disabling (SRD) mask (0xC0). Region 1 locks the variable data workspace to Execute-Never (XN) and Normal Non-Cacheable modes, while Region 4 maps a 128MB Device Memory region starting at 0x58000000 to whitelist peripherals. Symmetrically, the Cortex-M7 core deploys a matching MPU profile that restricts its own access to the SRAM4 safety sectors as strictly Read-Only and Execute-Never (XN), preventing cross-core thread memory corruption. * **ZERO-LATENCY INTER-CORE SIGNALING (HSEM)**: Traditional software polling and scheduling loop overhead are entirely eliminated. The firmware utilizes the physical hardware semaphore peripheral (HSEM) matrix. Upon completing an evaluation loop pass, the Cortex-M4 core fires an atomic latch token to HSEM Gate 0, instantly triggering a hardware HSEM1_IRQHandler vector interrupt inside the Cortex-M7 pipeline to awaken it out of low-power sleep (WFI) exactly when new data settles. * **ZERO-RAM-WRITE ESCAPE PATH & FAIL-SAFE MECHANICS**: The early assembly startup layers utilize compiler-driven section geometry padding (. = ALIGN(4)) to execute maximum-burst memory clearing loops that land precisely on section margins. Dynamic stack-overflow verification loops check the live stack register (sp) against an absolute global anchor constant (_sstack). Upon boundary breach detection, the core bypasses all volatile memory modifications and deploys an atomic assembly hardware store to the Bit Set/Reset Register (VXI_GPIOG_BSRR) to instantly latch emergency bypass pneumatics and gravity blast gates, freezing the CPU via a low-power while(1) { __WFI(); } loop to gracefully isolate a compromised core. * **PARALLEL-SAFE BUILD ENGINE & SYNCHRONIZED DEPLOYMENT**: The unified Makefile provides an explicit dependency graph supporting multi-threaded concurrent compilation while tightly mirroring structural optimization flags (-O2) across compilation and final link passes to ensure absolute symbol preservation. Post-build auditing targets invoke readelf to mathematically verify security boundaries at compile time. OpenOCD and GDB scripting profiles automate dual-port SWD Coresight DAP connections to flash, verify, and debug both targets independently over ports 3333 and 3334. -------------------------------------------------------------------------------- **REPOSITORY FILE MANIFEST** --------------------------------------------------------------------------------* Makefile: Parallel-safe dual-core cross-compilation build engine. * README.md: Descriptive repository operational manifest. * LICENSE: Standard MIT open-source data reuse permission ledger. * vxi_whitepaper.txt: Certified structural white paper tracking multi-core invariants. * tools/vxi_sys_flash.cfg: Master OpenOCD deployment and SWD target flashing script. * tools/gdbinit.gdb: Multi-core synchronized session breakpoint tracking profile. * tools/deploy.txt: Formal technical commissioning guidelines and terminal cheat sheets.* core_m4_safety/: Security domain core folder containing: - src/safety_core_m4.c: Type-safe deterministic checking loops and main wrapper targets. - src/mpu_config_m4.c: Multi-domain peripheral whitelisting and 3-slot MPU sandboxing engine. - inc/vortex_ion_insitu.h: Cache-line balanced telemetry array blocks and absolute register mappings. - linker_sram4.ld: Absolute memory layout map preventing binary zero-padding explosions. - startup_stm32h747_m4.s: Low-latency assembly vector loader and weak interrupt binding arrays. * core_m7_app/: Application domain core folder containing: - src/main_m7.c: Hardware-driven interrupt cycle cache flushes and master clock tree release sequence. - src/mpu_config_m7.c: Hardware-level sandboxing module blocking application-side safety core overwrites. - linker_flash.ld: Master 16KB stack application layer flash configuration layout script.- startup_stm32h747_m7.s: High-performance master application core boot vector assembly layout.