Neuromorphic_4Bit_Adder_CMOS
收藏IEEE2026-04-17 收录
下载链接：
https://ieee-dataport.org/documents/neuromorphic4bitaddercmos
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资源简介：
This dataset contains simulation schematics, layout files, and benchmarking results for RCA, CLA, and TLA adder architectures. It includes DSCH schematic files and MicroWind layout designs, along with tabulated performance metrics for delay, power, and area. The data supports reproducibility and comparative analysis of threshold logic-based neuromorphic designs, and complements the findings presented in the associated manuscript.
提供机构：
Abdul Rahman
