Underlying data for article "Impact of Fabrication Defects on FPGA Logic Usin...

Synthesis results from a modified, defect aware, Verilog-To-Routing synthesis flow. These result files were derived from the MCNC20 benchmarks synthesized on various...本数据集为经改进的缺陷感知型Verilog到布线（Verilog-To-Routing）综合流程所生成的综合结果。本次所用的结果文件均源自针对各类对象完成综合的MCNC20基准测试集。