A Low-Power Multicore ASIC CNN Accelerator with Dual Memory Banking and Hierarchical FSM-Based Control

This dataset contains the complete experimental and post-layout analysis data supporting the results presented in the manuscript entitled “Low-Power Multicore ASIC CNN Accelerator for Embedded and Automation-Oriented Systems”. The data were generated during the design, implementation, and evaluation of a low-power convolutional neural network (CNN) accelerator implemented in a 180 nm CMOS technology. The dataset includes all numerical values used to generate tables and figures reported in the manuscript. Power consumption data capture dynamic, leakage, and total power with and without FSM-controlled clock gating. Area utilization data provide a detailed breakdown of major functional blocks, including the hybrid MAC core array, dual memory bank subsystem, hierarchical FSM control logic, and routing overhead. Performance-related data include operating frequency, throughput scalability with core count, energy efficiency, and energy per operation. Timing analysis data comprise critical path delay distributions and timing slack values obtained from post-layout static timing analysis, demonstrating robust timing closure and deterministic behavior. Additional datasets report area–power trade-off comparisons, core utilization trends, and frequency-dependent energy characteristics. All data are provided in both a consolidated Excel file and individual CSV files to facilitate transparency, reproducibility, and reuse. The datasets are intended for researchers working in ASIC design, hardware accelerators, embedded systems, and energy-efficient AI computing.