Tensor Seeks Layout Finding the Right Memory Layout for ML Compilers

This dataset contains comprehensive experimental results and benchmark configurations for evaluating layout selection techniques in ML compilers targeting AWS Trainium hardware. The data includes: Experimental Performance Metrics: End-to-end compilation metrics comparing greedy search algorithms against baseline approaches across 32 model architectures Raw compilation logs capturing detailed execution traces for both greedy and baseline implementations Performance measurements including compilation time, memory usage, and optimization effectiveness Benchmark Specifications: Model configurations spanning Transformers, Large Language Models (LLMs), Mixture-of-Experts architectures, and multimodal models sourced from HuggingFace Test parameters defining input shapes, batch sizes, and compilation settings Formal specifications for three algorithmic approaches: treewidth-based dynamic programming, MaxSAT encoding, and greedy search with randomization Supporting Data: Cost model interface specifications for ML compiler frameworks Layout verification pass specifications for compiler pipelines Algorithm implementation artifacts in C++ and Python The dataset enables reproducibility of the paper's experimental evaluation, demonstrating the effectiveness of different layout selection strategies for tensor operations in ML compilation. All data was collected through systematic benchmarking on AWS Trainium hardware using the Neuron SDK compiler infrastructure.