Gate-Level RTL Description of the Glitch Optimized Multipliers

This paper presents a novel implementation schemeof the essential circuit blocks for high performance, full-precisionBooth multipliers leveraging a hybrid logic style. By exploitingthe behavior of parasitic capacitance of MOSFETs, a carefullyengineered design style is employed to reduce dynamic power dissipationwhile improving the glitch immunity of the circuit blocks.The circuit-level techniques along with the proposed signal-flowoptimization scheme prevent the generation and propagationof spurious activities in both partial-product and adder-treestages. Two full-precision Booth multipliers built from proposedstrategies were compared to the state-of-the-art versions knownfrom literature by means of extensive post-layout simulationsin 65-nm CMOS technology. The proposed versions on averagedemonstrated up to 10% and 30% power savings in general.

本文提出了一种新颖的实现方案，该方案针对高性能、全精度Booth乘法器中的基本电路模块，采用了混合逻辑风格。通过利用MOSFET寄生电容的行为，采用精心设计的方法以降低动态功耗，同时提高电路模块的抗干扰能力。电路级别的技术以及所提出的信号流优化方案防止了在部分积和加法树阶段产生和传播虚假活动。通过在65nm CMOS技术中进行广泛的布局后仿真，基于所提出策略构建的两个全精度Booth乘法器与文献中已知的最新版本进行了比较。平均而言，所提出的版本在一般应用中实现了高达10%和30%的功耗节省。