Data for: Investigation of the Stepped Split Protection Gate L-Trench SOI LDMOS with Ultra-Low Specific On-Resistance by Simulation

Fig.3. Output capacitance versus effective gate voltage, VG-VT.
Fig. 4. Comparison of transfer characteristics among the three structure at Vds = 25 V.
Fig. 5. Thermal characteristics curves of (a) Con. LDMOS, TG LT LDMOS, and SSG LT LDMOS surface temperature characteristics along the drift region. (b) Temperature as a function of Tox thickness variation.
Fig. 6. The relationship between drain voltage and current at breakdown. equi-potential contours of three devices, the proposed device, BV = 117 V, Con. LDMOS, BV = 101 V and TG LT LDMOS, BV = 102 V is shown as an insert.
Fig. 7. The dependence of the Nd as a function of the BV and Ron,sp.
Fig. 8. shows the influence of the Wt on the BV and FOM of the SSG LT LDMOS. The inset shows the effect of the left trench width on the BV of the device.
Fig. 9. The effect of the thickness variation of the buried oxide layer on the BV of the device at the breakdown (a) The effect of Tox thickness variation on BV (Wt=0.5µm). (b) The charge concentration on both sides of the buried oxide layer corresponding to different buried layer thicknesses.
Fig. 10. BV, Ron,sp and FOM of SSG LT LDMOS versus PG oxide width for two different PG depths. (a) Influences of TG2 on BV and Ron,sp. (b) Influences of TG3 on BV and FOM.
Fig. 11. Gate charge with a turn-on voltage of 60 V and the device length of 4 μm. The inset on the left is the gate charge test circuit, and the right side is the TG LT LDMOS, SSG LT LDMOS on-state simulation.
Fig. 13. Ron,sp versus the BV for SSG LT LDMOS and other different types of LDMOS.

图3. 输出电容与有效栅压 VG-VT 的关系图。
图4. 在 Vds = 25 V 下，三种结构转移特性的比较。
图5. （a）常规LDMOS、TG LT LDMOS和SSG LT LDMOS沿漂移区域的表面温度特性曲线；（b）温度随 tox 厚度变化的函数曲线。
图6. 在击穿时，漏电压与电流之间的关系，显示三个设备（包括所提出设备，BV = 117 V，常规LDMOS，BV = 101 V 和 TG LT LDMOS，BV = 102 V）的等势线轮廓，如图中插入部分所示。
图7. Nd 随 BV 和 Ron,sp 的函数关系。
图8. Wt 对 SSG LT LDMOS 的 BV 和 FOM 的影响。插入部分显示了左侧沟槽宽度对器件 BV 的影响。
图9. 埋氧化物层厚度变化对器件击穿时 BV 的影响（a）Tox 厚度变化对 BV 的影响（Wt=0.5µm）；（b）对应不同埋层厚度的埋氧化物层两侧的电荷浓度。
图10. SSG LT LDMOS 的 BV、Ron,sp 和 FOM 与 PG 氧化物宽度的关系，对于两种不同的 PG 深度。（a）TG2 对 BV 和 Ron,sp 的影响；（b）TG3 对 BV 和 FOM 的影响。
图11. 具有开启电压 60 V 和器件长度为 4 μm 的栅电荷。左侧的插入部分是栅电荷测试电路，右侧是TG LT LDMOS、SSG LT LDMOS 的导通状态仿真。
图13. SSG LT LDMOS 和其他不同类型LDMOS的 Ron,sp 与 BV 的关系。