Data and code underlying the research of: SRIF-ADC for CIM accelerators
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This targets neuromorphic and general-purpose arithmetic applications. A scalable and reliable integrate and fire circuit ADC (SRIF-ADC) design for CIM architectures is presented, suitable for stringent power and area constraints. Techniques to stabilize the node receiving analog in-puts are implemented that allow more rows to be activated at the same time, thereby improving the scalability in terms of higher parallelism of operations. A self-timed variation-aware design approach is introduced along with design measures to drastically reduce the read disturb of memristor devices. In addition, a compact, built-in sample-and-hold circuit to replace the typically used large-sized capacitance is present along with a built-in weighting technique to alleviate the need for post-processing when combining outputs of different bit significance. This dataset includes schematic netlist files, raw data on the Excel sheets for latency and power estimations/simulation results, and Matlab codes for generating the graphs and figures in the associated publication.
本数据集面向神经形态计算与通用算术类应用。本文提出了一种面向存算一体（Compute-In-Memory, CIM）架构的可扩展可靠积分发放型模数转换器（integrate-and-fire circuit ADC, SRIF-ADC）设计，可适配严苛的功耗与面积约束条件。研究实现了针对模拟输入接收节点的稳定化技术，能够支持同时激活更多阵列行，进而提升操作并行度维度的可扩展性。本文引入了自定时变化感知设计方法，并搭配可大幅降低忆阻器（memristor）器件读干扰的设计手段。此外，本数据集采用紧凑的内置采样保持电路替代传统常用的大容量电容，并内置加权技术，以消除不同比特位输出合并时的后处理需求。本数据集包含原理图网表文件、用于延迟与功耗评估/仿真结果的Excel原始数据表，以及用于复现相关发表论文中各类图表的Matlab代码。
