Investigation of Gate Dielectric Interface on Contact Resistance of Short Channel Organic Thin Film Transistors (OTFT)

This dataset presents a detailed numerical investigation into the role of interfacial engineering in organic thin-film transistors (OTFTs) using hybrid and single-layer dielectric configurations. The simulations were carried out using the 2D Silvaco ATLAS tool to explore the electrical behavior of OTFTs with Al₂O₃ (high-k), PVP (low-k), and hybrid Al₂O₃/PVP dielectric stacks. The study primarily focuses on optimizing the dielectric interface to reduce contact resistance and improve overall device performance in short-channel devices with a channel length of 1 μm.High-k Al₂O₃ reduces threshold voltage but introduces higher leakage current and contact resistance, while low-k PVP helps suppress leakage current at the cost of reduced mobility. The hybrid Al₂O₃ /PVP dielectric configuration combines the benefits of both materials, leading to improved interface quality and electrical performance. The optimized hybrid dielectric reduced contact resistance to 4.84 KΩ·cm², as extracted from V_DS–I_D characteristics at a gate bias of −2 V. Additionally, PVP thickness variation from 2.4 nm to 4.2 nm demonstrated reduced trap densities and enhanced mobility.Hysteresis behaviour was analysed via C–V sweeps from −3 V to +3 V to assess charge trapping characteristics. The findings emphasize the importance of precise control over the dielectric stack in enhancing the performance of flexible and low-power OTFT-based electronic devices.