The JPL Snapdragon Co-Processor: A compact high-performance computer for spaceflight applications

Following in the footsteps of the resounding success of the Ingenuity Mars Helicopter which was powered by a Qualcomm® SnapdragonTM 801 system-on-chip (SoC), the Jet Propulsion Laboratory has continued its investments into high-performance spaceflight computers based on Qualcomm’s Snapdragon line of SoCs. One significant achievement of these efforts is the development of the JPL Snapdragon Co-Processor (SCP), a small form-factor computer for spaceflight applications featuring the automotive-grade Snapdragon SA8155P SoC. The technology readiness level (TRL) of the SCP was raised to TRL- 6 in January 2024. The SCP is currently being included in two upcoming CubeSat-based on-orbit technology demonstration missions and is under consideration as a computer vision processor for missions up to and including class-B.The Snapdragon SA8155P features an octa-core Arm® CPU cluster with four Cortex® A-76 and four Cortex A-55 cores, a graphics processing unit (GPU) capable of 898 GFLOPs (32-bit floating-point), and a cluster of 4 HexagonTM DSP cores. The SCP board is outfitted with 16 GB of RAM, 128 GB of non- volatile Flash memory, and 2 Mb FRAM. The external interfaces of the SCP are two USB 3.1 Gen2 ports, a 4x4 lane MIPI Camera Serial Interface connector, and a 200-pin space-grade mezzanine connector featuring three total PCI Express lanes, an RGMII interface to support Gigabit Ethernet, and low-speed UART, GPIO, JTAG, and SPI connections. To utilize the interfaces on the mezzanine connector, JPL has developed a variety of custom carrier cards for the SCP, ranging from the advanced and high- performance line of Swift Processor Modules to a dedicated SCP carrier card for CubeSat applications.In this paper, we present a detailed overview of the SCP design, its capabilities, and its interfaces to the spacecraft bus. We describe the available options to integrate the SCP into a space- craft using the currently available and in-development carrier boards as examples. We comment on the software support and past and future JPL software benchmarking and porting efforts. Finally, we comment on the TRL-6 test campaign and give a brief outlook of the future of the SCP for JPL missions and the wider spaceflight community.

继采用高通®骁龙™ 801系统级芯片（System-on-Chip，SoC）的机智号火星直升机取得圆满成功后，美国喷气推进实验室（Jet Propulsion Laboratory，JPL）持续投入研发基于高通骁龙系列系统级芯片的高性能航天计算机。此项研发的一项重要成果，便是JPL骁龙协处理器（Snapdragon Co-Processor，SCP）——一款面向航天应用的紧凑型计算机，搭载车规级骁龙SA8155P系统级芯片。该协处理器的技术成熟度等级（Technology Readiness Level，TRL）已于2024年1月提升至TRL-6。目前，该协处理器已被纳入两项即将开展的基于立方体卫星（CubeSat）的在轨技术演示任务，同时也被考虑作为B级及以下航天任务的计算机视觉处理器。
骁龙SA8155P搭载八核Arm® CPU集群，包含4颗Cortex® A-76核心与4颗Cortex A-55核心，配备算力达898 GFLOPs（32位浮点）的图形处理器（Graphics Processing Unit，GPU），以及由4颗Hexagon™ 数字信号处理器（Digital Signal Processor，DSP）核心组成的集群。该协处理器板载16 GB随机存取存储器（Random Access Memory，RAM）、128 GB非易失性闪存以及2 Mb铁电随机存取存储器（Ferroelectric Random Access Memory，FRAM）。其外部接口包含2个USB 3.1 Gen2端口、1个4x4通道MIPI摄像头串行接口（MIPI Camera Serial Interface）连接器，以及1个200针航天级夹层连接器：该连接器总计支持3条PCI Express（PCIe）通道、用于支持吉比特以太网的简化吉比特介质独立接口（Reduced Gigabit Media Independent Interface，RGMII），以及低速通用异步收发传输器（Universal Asynchronous Receiver/Transmitter，UART）、通用输入输出（General Purpose Input/Output，GPIO）、联合测试行动小组（Joint Test Action Group，JTAG）与串行外设接口（Serial Peripheral Interface，SPI）连接。
为适配夹层连接器的各类接口，JPL为该协处理器开发了多款定制载板，覆盖从高性能先进Swift处理器模块产品线，到面向立方体卫星应用的专用SCP载板等多种类型。
本文将详细概述SCP的设计方案、性能参数及其与航天器总线（Spacecraft Bus）的接口规范；以现有及在研载板为例，阐述将SCP集成至航天器的可行方案；讨论其软件支持体系，以及JPL过往及未来的软件基准测试（Benchmarking）与移植（Porting）工作；最后针对TRL-6级测试活动进行说明，并简要展望SCP在JPL航天任务乃至更广泛航天领域的未来发展前景。

搜集汇总

背景与挑战

背景概述

该数据集详细介绍了JPL Snapdragon协处理器（SCP），这是一种基于高通Snapdragon SA8155P SoC的紧凑型高性能空间计算机，已于2024年1月达到TRL-6技术成熟度等级。SCP配备八核Arm CPU、高性能GPU和DSP，支持多种外部接口，目前正被纳入两个CubeSat在轨技术演示任务，并考虑用于B级任务中的计算机视觉处理。