Neutron-induced Single Event Upsets in SRAMs for Terrestrial Enviroment

As the technology node of CMOS electronic devices scales down, they become more and more susceptible to bit upsets caused by single particles impinging on the device, neutrons being part of them. We plan to measure the sensitivity of various synchronous random access memories (SRAM) to neutron generated bit upsets. In particular, we intend to test SRAM based FPGAs. This will provide us an excellent opportunity to compare experimental results to our theoretical models of calculating neutron single event upset (SEU) sensitivity based on heavy ion irradiation data. In addition, we intend to test the SRAM of a novel system on a chip (SoC) designed for ultra low power.