Efficient and scalable 3D-FFT heterogeneous computing architecture dataset

The file of "Experimental test data.xlsx" contains two sheets. The "Transmission Bandwidth" sheet provides the number of clock cycles required for data exchange between global memory and local memory measured experimentally under different conditions, and further calculates the actual data transmission bandwidth at system frequencies of 250MHz and 300MHz. The "Time Consumption" sheet provides the number of clock cycles required to complete 3D-FFT with different numbers of FFT kernels, and further calculates the computing power, as well as the performance improvement of the designed architecture compared to CPU and other FPGA solutions. The file of "Original data of the matrix 64x64x64.txt" is the original data of the matrix 64x64x64, which used to execute 3D-FFT computation under size of 64x64x64.The file of "Original data of the matrix 128x128x128.txt" is the original data of the matrix 128x128x128, which used to execute 3D-FFT computation under size of 128x128x128.The file of "Software computational result of the matrix 64x64x64.txt" is the software computational result of the matrix 64x64x64, which generated by python library function using original data of the matrix 64x64x64.The file of "Software computational result of the matrix 128x128x128.txt" is the software computational result of the matrix 128x128x128, which generated by python library function using original data of the matrix 128x128x128.The file of "Hardware computational result of the matrix 64x64x64.txt" is the hardware computational result of the matrix 64x64x64, which generated by FPGA using original data of the matrix 64x64x64.The file of "Hardware computational result of the matrix 128x128x128.txt" is the hardware computational result of the matrix 128x128x128, which generated by FPGA using original data of the matrix 128x128x128.