"NPU Chip Blueprint Specifications and Performance Benchmarks: JRW Technologies and NPU Blueprints Dataset"
收藏DataCite Commons2026-05-01 更新2026-05-03 收录
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https://ieee-dataport.org/documents/npu-chip-blueprint-specifications-and-performance-benchmarks-jrw-technologies-and-npu
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资源简介：
"This dataset presents a comprehensive collection of neural processing unit (NPU) chip blueprint specifications and performance benchmarks compiled from two complementary sources: JRW Technologies and NPU Blueprints. The dataset encompasses 10 distinct chip designs targeting edge AI, IoT, and smart building applications, fabricated across leading semiconductor foundries including TSMC, GlobalFoundries, and Samsung. Each chip entry includes architecture type, process node, die area, power consumption, inference throughput (TOPS), memory bandwidth, supported frameworks, target use cases, and licensing information. JRW Technologies contributes 5 custom silicon designs ranging from microcontrollers to high-performance AI accelerators. NPU Blueprints contributes 5 production-ready RTL blueprints with no NRE fees, priced from $2,600 to $8,200 for one-time licensing. This dataset is intended to support researchers, chip designers, EDA tool developers, and procurement engineers evaluating AI inference hardware for embedded and edge deployments. Data is provided in CSV and JSON formats with a detailed README documenting field definitions and methodology."
提供机构：
IEEE DataPort
创建时间：
2026-05-01
