DET Flip Flop Usage with Commercial Cad Tools (Synthesis, P&R and Cell Characterization)

A novel ultra-low-voltage (ULV) Dual-EdgeTriggered (DET) flip-flop based on the True-Single-PhaseClocking (TSPC) scheme is presented in this paper. Unlike Single-Edge-Triggering (SET), Dual-Edge-Triggering has the advantage of operating at the half-clock rate of the SET clock. We exploit the TSPC principle to achieve the best energy-efficient figures by reducing the overall clock load (only to 8 transistors) and register power while providing fully static, contention-free functionality to satisfy ULV operation. The proposed DET design only requires 28 transistors, which is the lowest number reported among the state-of-the-art dual-edge designs. At 0.5V near-Vth level in 65nm bulk CMOS technology, the proposed DET-FF demonstrates up to 25-39% and 16-42% of energy efficiency at 0% and 100% data activity rates compared to the most reliable DET-FFs when measured at cell level. Moreover, for the first time, we provide a VLSI integration methodology with design automation support to use DET flip-flops with commercial CAD tools. From integration and post layout simulations, we observed energy savings upto 43% for a 320-bit shift register and upto 28% for a RISC-V processing core at near-VTH and at nominal VDD levels, respectively. This data package containes scripts, automated tool support for the DET flip-flop integration into larger digital designs.