Characterization of a Low-Cost FPGA-based Time-to-Digital Converter with Maximized Readout Speed

This dataset reports the specifications of a low-cost FPGA-based TDC whose readout speed is maximized. The evaluated TDC is composed of a toggling input stage to shape the hit signal and maximize the readout speed, a coarse counter to count the number of clocks between start and stop signals, a tuned tapped delay line to achieve high resolution, a dual-mode counter-based encoder to convert the output of the delay line to a binary number, a controller to determine the encoding mode, and a bin-width calibration to improve the TDC performance. To measure the exact bin widths and calculate the DNL and INL of the TDC, the code density test that is a statistical estimation approach, is hired.