architect-ubc-capstone/rtl-augmented

--- license: mit task_categories: - text-generation tags: - rtl - verilog - bug-fix - sft size_categories: - 1K<n<10K --- # RTL Bug Fix — Augmented Dataset Auto-generated dashboard snapshot (2026-03-20T10:46:42). ## Overview | Metric | Value | |--------|-------| | Total problems | 1,205 | | Repos with data | 15 / 80 | | Modules augmented | 145 | | Bug types | 8/8 | | Augmentation success | 54.9% | ## Coverage  ## Distribution   ## Augmentation Health  ## Topic Coverage  ## Warnings - scarv_xcrypto: 0 problems from 36 attempts — likely systematic sim issue - splinedrive_kianRiscV: 0 problems from 13 attempts — likely systematic sim issue - AngeloJacobo_RISC-V: 0 problems from 17 attempts — likely systematic sim issue - missing_else_latch: underrepresented (75 problems, 6.2%) - signal_typo: underrepresented (30 problems, 2.5%) - unconnected_port: underrepresented (45 problems, 3.7%) - No augmentation data for topics: amba, amba-axi, axi, axi4, chisel, computer-architecture, coremark, debugging-tools, design-verification, embedded-systems, fpga-soc, gplv3, in-order, nuclei, pipeline-processor, riscv-linux, riscv32, rv32im, sdram, soft-core, systemc, uvm, verilog-components, vhdl, vivado, wishbone, wishbone-bus, zipcpu - 66/80 discovered repos have zero augmentation data