Dataset of 'An 8-channel, 46-ps-precision TDC ASIC with improved vernier delay loop for STCF EMC'

This dataset is mainly intended to provide data support for 'An 8-channel, 46-ps-precision TDC ASIC with improved vernier delay loop for STCF EMC.' It primarily includes the test results of the TDC chip proposed in the paper, all the figures from the paper, and the raw data for some of the figures. The descriptions have been provided in the associated paper.