Area and power comparison for various synaptic plasticity circuits.
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*The biases are optimised for the hippocampal (first) data set and then the energy consumptions are measured.**This design has been implemented in a 90 nm CMOS process with a supply voltage of 0.6 V.***This design has been implemented in a 0.25 µm CMOS process, while power supply = 3.3 V has been equal to the other presented designs in this table.
创建时间：
2015-12-02
