High-speed Reconfigurable Multi-triggered Optical Chaotic D-latch and D-flip-flop Operations under Clock Synchronization

At present， most optical chaotic logic devices can only complete a single logic function， and can not meet the requirements of more complex logic functions for optical signal packet switching nodes in chaotic networks， so the related research of optical chaotic logic devices has shifted from basic logic to complex sequential logic. Optical chaotic latches and flip-flops， serving as the basic building blocks and memory units of optical chaotic sequential logic devices， can be integrated with combinational logic devices such as adders， subtractors， and multipliers to enable the realization of more advanced modules， including shift registers， counters， and random-access memories. However， previous studies have predominantly focused on clock-free single-trigger flip-flops with identical triggering conditions， exhibiting limited confidentiality and weak noise immunity. Current research on implementing flip-flops using chaotic lasers remains relatively scarce.Based on optical injection cascaded VCSELs chaotic system， electro-optic modulation theory and polarization bistability， we successfully implement high-speed reconfigurable multi-triggered optical chaotic D-latch and D-flip-flop operations under clock synchronization. Firstly， we numerically investigate the evolution of dynamic states for both polarization component （x-PC and y-PC） in the strongly injected VCSEL2 with respect to the optical injection amplitude and applied electric field， as well as the polarization bistability as a function of the optical injection amplitude. We observe that the polarization switching behavior of VCSEL2 can be induced by alternating the applied electric field between 11 kV/mm and 25 kV/mm. When E0=11 kV/mm and Einj exceeds 4.7， the y-PC is completely suppressed by the x-PC， and the x-PC assumes absolute dominance. If E0=25 kV/mm and Einj also exceeds 4.7， y-PC dominates， while the x-PC is completely suppressed. And we propose a novel mean-value comparison mechanism to demodulate the x-PC and y-PC from VCSEL2 for the acquisition of logic outputs. Then we demonstrate the implementations of reconfigurable multi-triggered optical chaotic D-latches and D-flip-flops that are synchronized by a clock signal and response for as short as 10 ps bit time. By calculating the dependence of the success probability of D-latches and D-flip-flops on bit time and optical injection strength， we discover that when the optical injection strength kx （ky） is less than 9 ns⁻¹， the success probability of the D-latches is below 1， indicating the occurrence of bit errors in the logic output. And under the premise of a success probability of 1， increasing the optical injection strength can effectively reduce the lower limit of bit time. When the optical injection strength exceeds 43 ns-1， the lower limit of bit time can be stably reduced to 3 ps， achieving a computational speed of up to 333.3 Gb/s. Finally， by evaluating the impact of spontaneous emission noise on the reliability of D-latches and D-flip-flops， we demonstrate that the success probability remains unity even at a noise strength as high as 1.6×1010. Even the noise strength increases to 5×1010， the success probability remain above 0.98. These results demonstrate that the D-latches and D-flip-flops exhibit outstanding characteristics including high-speed operation， strong noise immunity， and flexible reconfigurability， which hold significant application and reference value in chaotic secure communication networks.