Data and code underlying the research of: CCO-ADC for CIM Acclerators

This targets image classification applications. This work presents a memory-periphery co-design to perform accurate A/D conversions of analog matrix-vector-multiplication (MVM) outputs. A novel scheme is introduced where select-lines and bit-lines in the memory are virtu- ally fixed to improve conversion accuracy and aid a ring-oscillator-based A/D conversion, equipped with component sharing and inter-matching of the reference blocks. In addition, we deploy a self-timed technique to further ensure high robustness addressing global design and cycle-to-cycle variations. The concept is demonstrated using a 4Kb CIM chip prototype using resistive bitcells on TSMC 40nm CMOS technology. This dataset includes schematic netlist files, chip photos, raw data on the Excel sheets for latency and power estimations/simulation results, and Matlab codes for generating the graphs and figures in the associated publication.

本研究面向图像分类应用场景。本工作提出一种存储器-外设协同设计方案，可实现模拟矩阵向量乘法（matrix-vector-multiplication, MVM）输出结果的高精度模数转换。本文引入一种全新的设计策略：将存储器内的选择线与位线进行虚拟固定，以提升转换精度，并辅助基于环形振荡器的模数转换流程，该流程集成了组件共享与参考模块相互匹配机制。此外，本方案采用自定时技术，可进一步提升鲁棒性，以应对全局设计差异与周期间波动。该设计理念通过一款采用台积电40纳米CMOS工艺、搭载阻性存储单元的4千比特存算一体（Compute-In-Memory, CIM）芯片原型得到验证。本数据集包含原理图网表文件、芯片实物照片、用于延迟与功耗估算及仿真结果分析的Excel表格原始数据，以及用于生成相关发表论文中各类图表的Matlab代码。